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Design of Core Based System-On-Chip Using Interfaced Cores and Routers in Network-On-Chip

Swati Balpande, Rupali Suraskar

Abstract


Abstract

Network-On-Chip (NOC) architectures consist of heterogeneous cores connected through an interconnection network. The communication between the nodes is achieved by routing packets rather than wires. NOC has emerged as a new paradigm for designing core based System-on-Chip (SOC). Network-on-Chip is seen as a scalable solution facilitating the development of system-on-chip with an increasing number of IP cores. The idea of using on chip packet switched networks for interconnecting a large number of IP cores is very practical for designing complex SoCs since it gives possibility of not only reusing IP cores but also the interconnection infrastructure. The success of NOC design relies greatly on the standardization of the interfaces between IP cores and routers. The core may have different frequency where, as the router may also operate at different frequency as per design. So, there is possibility of losing some data due to improper synchronization. In this paper, we proposed the design of XY-router to make IP core compatible to network switch, enabling communication between them. We also propose the GALS style of communication which has been implemented in NOC by using XY-router and parallel processing for optimized low delay, power and area.  

Keywords: System-on-Chip, Network-on-Chip, XY-routing algorithm, parallel processing

Cite this Article

Swati Balpande, Rupali Suraskar. Design of Core Based System-On-Chip Using Interfaced Cores and Routers in Network-On-Chip. Journal of Mobile Computing, Communications & Mobile Networks. 2017; 4(3): 17–24p.



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