An Optimized FIR Filter Architecture Using Approximate Radix-8 Booth Multiplier

Abstract

This paper presents an optimized FIR filter architecture using approximate radix-8 Booth multiplier. The radix-8 Booth multiplier is slow due to the complexity of generating the odd multiples of the multiplicand. Hence, for calculating the sum of 1x and 2x of a binary number x, an approximate 2-bit adder is deliberately designed. This adder requires a small area, a low power and a short critical path delay. Subsequently, the less significant section of a recoding adder is implemented by the 2-bit approximate adder for generating the triple multiplicand. A 16 bit approximate radix-8 Booth multiplier is then designed using the approximate recoding adder without the truncation of a number. The proposed approximate multipliers are faster and more power efficient than the accurate Booth multiplier. An optimized FIR filter combining the advantage of both direct form I and transposed structure is designed. Such a hybrid filter has critical path much less than that of direct form FIR filter and less area than that of the transposed form.