Efficient CRC Implementation in 10G Ethernet and DigRF V4 Protocol

Abstract

Abstract

CRC is the most commonly used error detection technique in most of the digital logic designs and communication links, so as to confirm whether the received digital message has got any error or not, and whether it has been corrupted in the transmission in between the different modules of the design or not. The protocols or the devices which are required to be operated at higher speed like 10G Ethernet operate at 156.25 MHz, DigRF V4 (a digital interface standard between baseband IC and RF IC), operate at 100 MHz of clock speed; there comes the requirement for faster CRC implementation. Many types of techniques for the same purpose have been developed starting from serial CRC to parallel CRC with more and more improvement in parallel CRC by developing different techniques in the parallel CRC implementation. There is also a possibility that the packet or the frame in these protocols does not have length equal to the interface width; in that case, parallel CRC implementation becomes less efficient. So, there should be a solution for this as well. The proposed work gives a solution for these two problems by first implementing the parallel CRC architecture because of its higher speed as compared to serial CRC, and it also takes care of the case of packet length not being equal to or a multiple of the interface width. It uses only three configurations for CRC-32 to be used as CRC-32 (4), CRC-32 (2) and CRC-32 (1), to cover all the corner cases of byte presence in the complete packet, where 4, 2 and 1 are the number of bytes to be transmitted and are actually present in the packet or frame.

Keywords: 10G, CRC, LFSR

Cite this Article

Priyanka Aggarwal, Neeraj Kr. Shukla, Simran Choudhary. Efficient CRC Implementation in 10G Ethernet and DigRF V4 Protocol. Journal of Web Engineering & Technology. 2017; 4(3): 19–24p.