Review on Multicore Processors

Arpita Srivastava, Priyanshi Agarwal



Multi-core processors based product servers recently progress toward becoming building obstructs for superior computing Linux bunches. The multi-core processors convey better execution to cost proportions in respect to their single-core predecessors through on-chip multi-threading. In any case, they exhibit challenges in growing superior multi-strung code. In this paper, we concentrate on the execution of various programming hindrance calculations on Intel Xeon and AMD Opteron multi-center processor based servers. Particularly, we investigate how distinctive memory subsystems, for example, shared transport or ccNUMA, and their store cognizance conventions impact the execution of obstruction calculations. What's more, we think about multi-threading programming overhead between OpenMP mandates and a privately created threading library that uses improved hindrance calculations alongside low overhead bolting primitives. We find that OpenMP usage gives superior run-time libraries combined with phenomenal compiler orders with overhead marginally more than the precisely upgraded library.

Keywords: Multi-core processors, on-chip multi-threading, API, SMP, AMD

Cite this Article

Arpita Srivastava, Priyanshi Agarwal. Review on Multicore Processors. Recent Trends in Parallel Computing. 2017; 4(1): 30–41p.

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