2:1 Multiplexer Using Different Design Styles: Comparative Analysis

Abstract

Abstract

This paper presents a comparative analysis of 2:1 multiplexer using different logic styles (transmission gate, pass transistor and CMOS logic), with three different technologies i.e. 45nm, 32nm and 16nm. Simulation is done using Synopsys HSPICE tool at 1V power supply. As a result, it is found that the least power is consumed by 2:1 multiplexer implemented using TGL. It consumes 99.7% less power than pass transistor logic and PTL consumes 99% more power than CMOS. Since multiplexer implemented by PTL utilizes minimum number of transistors, i.e., 2 ,therefore it is the area efficient logic circuit for 2:1 MUX but its performance is low as its output is somewhat distorted.

Abstract

This paper presents a comparative analysis of 2:1 multiplexer using different logic styles (transmission gate, pass transistor and CMOS logic), with three different technologies i.e. 45nm, 32nm and 16nm. Simulation is done using Synopsys HSPICE tool at 1V power supply. As a result, it is found that the least power is consumed by 2:1 multiplexer implemented using TGL. It consumes 99.7% less power than pass transistor logic and PTL consumes 99% more power than CMOS.Since multiplexer implemented by PTL utilizes minimum number of transistors, i.e., 2 ,therefore it is the area efficient logic circuit for 2:1 MUX but its performance is low as its output is somewhat distorted.