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Half Adder Using Different Design Styles: A Review on Comparative Study

Anju Rajput, Tripti Dua, Dr. Renu Kumawat, Dr. Avireni Srinivasulu



A half adder is a digital logic circuit that performs addition of two single bit binary numbers. Generally, in various types of processors, adders are used to perform arithmetic and logical operations .In this paper, working of half adder is analysed by designing it by using three different logic styles, i.e., CMOS logic, Transmission Gate Logic (TGL) and Pass Transistor Logic (PTL). The comparison has been made between the circuits on the basis of their power consumption and transistor count. Simulation of the circuits is carried out using HSPICE tool at 45 nm, 32 nm and 16 nm technologies at 1V power supply. After simulation it is observed that power consumption is lowest when the adder is implemented by transmission gate as compared to CMOS and PTL design styles whereas transistor count is minimum in case of PTL design style. It is also inferred that CMOS gives the best performance out of the three design styles.


Power dissipation, CMOS, pass transistor, transmission gate, transistor count

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