Implementation of Floating Point Multiplier Using Dadda Algorithm
Floating point multiplication is very useful in all the computation applications like in arithmetic operation, DSP application etc. To achieve higher speed of the mantissa, multiplication is done using Dadda multiplier which works on the basis of Dadda algorithm. Through this architecture we gain high speed with a maximum frequency and also reduce the number of gates compared to existing multipliers; and through floating point format it is possible to handle overflow or underflow conditions. This multiplier is implemented using verilog HDL and targeted for Spartan3A and 3ANFPGA and the comparison is done with the Xilinx floating point multiplier core.
Keywords: Dadda algorithm, floating point standard format, single precision, FPGA, VHDL
Cite this Article
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