A Survey on Various Study for SRAM Cell Topologies

Abstract

Abstract: In order to meet performance demands continuous derivative, the amount of on-chip memory or microprocessors and system-on-chip is increased. As much as 70% of the chip area is now given to the embedded memory, which is mainly realized by the static random access memory (SRAM). Due to the large size of the SRAM, their energy performance and leakage performance and leakage dominate total energy consumption of the chip. The leakage power being the major topic of concern in semiconductor industry is needed to be reduced to its lowest. Since the static power consumption and dynamic power consumption degrades the performance of the on chip devices due to high integration density. Therefore, the leakage reduction improves the efficiency of the on chip devices. Since, the memory structures are coupled through a large fraction of the region of a microprocessor chip. Due to the large on-chip memories approximately 90% of the SOC, reducing leakage current even in single cell cache, a large fraction of the total power can be decreased in integrated circuits. However, as CMOS technology continues to scale in the system of 45 nm to reduce the cost and dynamic power transistor, poses a number of challenges in the design of SRAM. In this paper, we address these challenges and propose solutions to the cell level and architecture level to increase performance and reduce leakage current, power consumption and improve reading speed SRAM cell in Nano-scale CMOS technologies.

Keywords: SRAM Cell, Lekage Current, CMOS, FinFET, Leakage Power

Cite this Article: Vaibhav Shrivastava, Nikhil Saxena. A Survey on Various Study for SRAM Cell Topologies. Journal of Software Engineering Tools & Technology Trends. 2019; 6(3): 1–8p.