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Design and Analysis of Low Power, High Speed 64-Bit Alu Using Efficient Technique

Sateesh kourav, Sunil Shah

Abstract


Abstract

The analysis of low power, high velocity a 64-cycle Arithmetic Logic Unit by effective methods Carry Look Ahead Technique utilizing VHDL language. The speed and zone of preparation boundaries are improved utilizing the convey look-forward strategy. It likewise lessens circuit intricacy. Number juggling rationale is a major structure square of the unit ALU. A convey look-forward joiner limits spread postponements by presenting more perplexing equipment. A convey look-ahead method improves speed by lessening the measure of time needed to decide bits. It likewise decreases the circuit intricacy. The proposed plan of the Arithmetic Logic Unit will play out the numerical, sensible, and moving tasks like Addition, Subtraction, Multiplication, Increment, Decrement, Logical AND, Logical OR, Logical XOR, and so forth within the computer. The efficient modules of the arithmetic logic unit are designed using Xilinx software and simulation results are verified on one platform employing a test bench.

 


Keywords


ALU, VHDL, ADD, SUB, MUL, CLA.

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