Implementation of Floating Point Multiplier Using Dadda Algorithm

Authors

  • Nithyashree S Department of Electronics and Communication, AIT, Bangalore, Karnataka, India
  • Karthik S. Department of Electronics and Communication, AIT, Bangalore, Karnataka, India

DOI:

https://doi.org/10.37591/jomtra.v3i1.643

Abstract

Floating point multiplication is very useful in all the computation applications like in arithmetic operation, DSP application etc. To achieve higher speed of the mantissa, multiplication is done using Dadda multiplier which works on the basis of Dadda algorithm. Through this architecture we gain high speed with a maximum frequency and also reduce the number of gates compared to existing multipliers; and through floating point format it is possible to handle overflow or underflow conditions. This multiplier is implemented using verilog HDL and targeted for Spartan3A and 3ANFPGA and the comparison is done with the Xilinx floating point multiplier core.

Keywords: Dadda algorithm, floating point standard format, single precision, FPGA, VHDL

Cite this Article
Nithyashree S, Karthik S. Implementation of Floating Point Multiplier Using Dadda Algorithm. Journal of Multimedia Technology & Recent Advancements. 2016; 3(1): 16–22p.

References

IEEE 754-2008. IEEE Standard for Floating-Point Arithmetic. 2008.

Mohamed Al-Ashrfy, Ashraf Salem, Wagdy Anis. An Efficient implementation of Floating Point Multiplier. IEEE Transaction on VLSI 978-1-4577-0069-9/11@2011 IEEE, Mentor Graphics.

Fagin B, Renard C. Field Programmable Gate Arrays and Floating Point Arithmetic. IEEE Transactions on VLSI. 1994; 2(3): 365–367p.

Shirazi N, Walters A, Athanas P. Quantitative Analysis of Floating Point Arithmetic on FPGA Based Custom Computing Machines. Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM’95). 1995; 155–162p.

Louca L, Cook TA, Johnson WH. Implementation of IEEE Single Precision Floating Point Addition and Multiplication on FPGAs. Proceedings of 83 the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM’96). 1996; 107–116p.

Jaenicke, Luk W. Parameterized Floating-Point Arithmetic on FPGAs. Proc. of IEEE ICASSP. 2001; 2: 897–900p.

Townsend Whytney J, Swartz Earl E. A Comparison of Dadda and Wallace Multiplier Delays. Computer Engineering Research Center, The University of Texas.

Lee B, Burgess N. Parameterisable Floating-point Operations on FPGA. Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems, and Computers. 2002.

Xilinx 13.4. Synthesis and Simulation Design Guide. UG626 (v13.4) Jan 19, 2012.

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Published

2016-04-26

Issue

Vol. 3 No. 1 (2016)

Section

Research Articles

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