3D-IC Partitioning and TSV Sharing Optimization Algorithm

Authors

  • M. Sarojini Department of Electronics and Communication Engineering, Thiagarajar College of Engineering, Madurai, Tamil Nadu, India
  • D. Gracia Nirmala Rani Department of Electronics and Communication Engineering, Thiagarajar College of Engineering, Madurai, Tamil Nadu, India

DOI:

https://doi.org/10.37591/jomtra.v3i2.753

Abstract

Recent technologies are in need of shorter vertical interconnects, thus forcing the integration technology from 2D to 3D. Because more than 50% of dynamic power consumption is due to interconnects. As a solution, 3D integration consists of stacking integrated circuits and connecting them with short vertical interconnects. TSV is used to vertically connect the hardware components in different dies stacked in 3D ICs. But in floor planning TSVs are very large when compared to the other circuit features and logic gates. The TSV count and its location are considered to be important. Hence, we have proposed a TSV sharing and optimization algorithms after 3D partitioning, which utilizes the information of data transfer from high-level synthesis and partitioning. Here, MediaBench benchmark is partitioned using HMETIS, which is a standalone program and uses the multilevel hypergraph partitioning algorithm. After partitioning, based on design complexity and bit width, word level sharing algorithm has been used. Our proposed algorithms have reduced the number of TSVs based on the constraints.

Keywords: TSV, HMETIS, partitioning, resource sharing, optimization

Cite this Article
Sarojini M, Gracia Nirmala Rani D, Divya Preethi G. 3D-IC Partitioning and TSV Sharing Optimization Algorithm. Journal of Multimedia Technology & Recent Advancements. 2016; 3(2): 13–17p.

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Published

2016-09-08

Issue

Vol. 3 No. 2 (2016)

Section

Research Articles

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