Performance Analysis of Junctionless SONOS Memory
DOI:
https://doi.org/10.37591/joosdt.v7i3.2630Keywords:
Silicon-Oxide-Nitride-Oxide-Silicon (SONOS), Junctionless (JL) memory, Silicon on Insulator (SOI), Fowler–Nordheim (FN), Shockley-Read-Hall (SRH), Silicon Nanowire (Si-NW), Equivalent Oxide Thickness (EOT).Abstract
Abstract
This paper presents the performance analysis of the JL SONOS device electrical characteristics of the two different types of device i.e., one built on BULK substrate and other over the SOI substrate. The difference in the properties and its related impact on the device performance will be discussed through physical interpretations and mathematical equations. Simulation of both devices is done by taking same device dimension and parameter to check the program and erase characteristics and compared on the basis of improved memory characteristics. In the memory device, variation occur in the characteristics of device, have been discussed. To achieve the required memory performance bulk doping is used as tunning parameter. The erasing efficiency of the JL bulk SONOS memory cell is better and JL SOI SONOS memory cell exhibits larger memory window within a specified program time.
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