Testability Techniques Used in Different Design Environment for Improving Fault Efficiency

Authors

  • Harshi Tomar Gautam Buddha University, Gautam Budh Nagar, Greater Noida, Uttar Pradesh, India
  • Sandeep Sharma Gautam Buddha University, Gautam Budh Nagar, Greater Noida, Uttar Pradesh, India
  • Navaid Zafar Rizvi Gautam Buddha University, Gautam Budh Nagar, Greater Noida, Uttar Pradesh, India

DOI:

https://doi.org/10.37591/rtpl.v3i1.669

Abstract

The paper provides an overview of automatic creation of test patterns using different design for testability techniques (DFT). The main intent is to collect the data from specification, design and completely different synthesis environment and then applying various test conditions which aims at to reduce the time required for test case generation and also to relieve the designers from much tedious task. Increasing size and complexity of digital designs has made essential to address critical verification issues at the early stages of design cycle. Therefore, automated verification tools are necessary at higher levels of abstraction. In this context, we have discussed different design for testability techniques for automatically generating test sequence for functional circuits at register transfer level (RTL). These techniques have many advantages and disadvantages so a comparison based on few parameters essential in the circuit is shown to improve the fault efficiency. Experimental results show robustness and reliability of these techniques as compared to other contemporary approaches in terms of fault coverage, fault efficiency, test generation, test application and area overhead.

Keywords: Testability Techniques, System on a Chip (SoC), Automatic Test Pattern Generation (ATPG), Design for Testability (DFT)

Cite this Article
Harshi Tomar, Sandeep Sharma, Navaid Zafar Rizvi. Testability Techniques Used IN Different Design Environment for Improving Fault Efficiency. Recent Trends in Programming languages. 2016; 3(1): 1–6p.

References

Obein MEJ, Ohtake S, Constrained ATPG for functional RTL circuits using F-Scan, in Test Conference (ITC), 2010, IEEE, International, Nov 2010, 1–10p.

Fallah F, Devadas S, Keutzer K, Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability, in Proc. Design Automation Conf. (DAC98), 1998, 528–533p.

Di Guglielmo G, Fummi F, Marconcini C, et al. EFSM Manipulation to Increase High-Level ATPG Efficiency, In Proc. of IEEE ISQED. 2006.

Alizadeh B, Fujita M, Early Case Splitting and False Path Detection to Improve High Level ATPG Techniques, in Circuits and Systems (ISCAS), 2011 IEEE International Symposium, May 2011, 1463–1466p.

Alizadeh B, Fujita M, Guided gate-level ATPG for Sequential Circuits using a High-Level Test Generation Approach, in Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific, Jan 2010, 425–430p.

Giuseppe Di Guglielmo, On the Validation of Embedded Systems through Functional ATPG, in Research in Microelectronics and Electronics, Istanbul, April 2008, 149–152p.

Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha, Satisfiability-based Test Generation for Nonseparable RTL Controller-datapath Circuits, IEEE T Comput Aided D. March 2006; 25(3): 544–557p.

Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha, TAO: Regular Expression-Based Register-Transfer Level Testability Analysis and Optimization, IEEE T VLSI Syst. Dec 2001; 9(6): 824–832p.

Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, et al. A Non-Scan DFT Method at Register-Transfer Level to Achieve Complete Fault Efficiency, in Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000, Asia and South Pacific, June 2000, 599–604p.

Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha, A Design-for-Testability Technique for Register-Transfer Level Circuits Using Control/Data Flow Extraction, IEEE T Comput Aided D. August 1998; 17(8): 706–723p.

Alizadeh B, Fujita M, HED: A Canonical and Compact Hybrid Word- Boolean Representation as a Formal Model for Hardware/Software Co-designs, in International Workshop on Constraints in Formal Verification (CFV07), 2007, 15–29p.

Alizadeh B, Fujita M, High Level Test Generation without ILP and SAT Solvers, in International Workshop on High Level Design Validation and Testing (HLDVT07), 2007, 298–304p.

Bijan Alizadeh, Mohammad Mirzaei, Masahiro Fujita, Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits, IEEE T Comput Aided D. May 2010; 29(5): 737–748p.

Lee D, Yannakakis M. Online Minimization of Transition Systems, in Proc. of ACM Symposium on the Theory of Computing, 1992, 264–274p.

Flextest: http://www.mentor.com/products/silicon-yield/logic_test/

Giuseppe Di Guglielmo, Franco Fummi Cristina, Marconcini Graziano Pravadelli, FATE: A Functional ATPG to Traverse Unstabilized EFSMs, in Test Symposium, 2006. ETS '06. Eleventh IEEE European, 179–184p, May 2006.

Wada H, Masuzawa T, Saluja KK, et al. A DFT Method for RTL Data Paths Achieving 100% Fault Efficiency under Hierarchical Test Environment, European Test Workshop, 1999.

Obein MEJ, Ohtake S, Fujiwara H, Constrained ATPG for Functional RTL Circuits using F-Scan, in Test Conference (ITC), 2010 IEEE International, Nov 2010, 1–10p.

Ho P.-H, Shiple T, et al. Smart Simulation using Collaborative Formal and Simulation Engines, in Proc. International Conf. on CAD (ICCAD00), 2000, 120–126p.

Masuzawa T, Wada H, Saluja KK, et al. A non-scan DFT Method for RTL Data Paths to Achieve Complete Fault Efficiency, Technical Report, Information Science Technical Report: TR98009, Nara Institute of Science and Technology, 1998.

Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu, Enhancing Reliability of RTL Controller-Datapath Circuits via Invariant-Based Concurrent Test, IEEE T Reliab. June 2004; 53(2): 269–278p.

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Published

2016-04-30

Issue

Vol. 3 No. 1 (2016)

Section

Research Articles

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